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Board Components
Table 2–1. Nios Development Board, Stratix Edition Components & Interfaces (Part 2 of 2)
Board Designation
SW8
SW9
SW10
LED0 – LED3
Clock Circuitry
Y2
J4
Name
CPU Reset button
Factory Config
button
Reset, Config
Configuration
status LEDs
Oscillator
External clock
Description
Push-button switch to reboot the Nios II processor configured
in the FPGA
Push-button switch to reconfigure the FPGA with the factory-
programmed reference design
Push-button switch to reset the board
LEDs that display the current configuration status of the
FPGA
50 MHz clock signal driven to FPGA
Connector to FPGA clock pin
input
Power Supply
J26
D34
DC power jack
Bridge rectifier
17 V DC unregulated power source
Power rectifier allows for center-negative or center-positive
power supplies
The sections that follow describe each component in detail.
Stratix II Device
(U60)
U60 is a Stratix II FPGA in a 672-pin FineLine BGA? package. Early
shipments of the Nios Development Board, Stratix II Edition included an
EP2S60F672C5 device. Some early boards used engineering sample parts,
indicated by “ES” after the part number. Later shipments of the board use
an EP2S30F672C5 device. Table 2–2 lists the device features.
Table 2–2. Stratix II Device Features (Part 1 of 2)
Feature
ALMs
Adaptive look-up tables (ALUTs)
Equivalent LEs
M512 RAM blocks
M4K RAM blocks
M-RAM blocks
Total RAM bits
DSP blocks
EP2S30
13,552
27,104
33,880
202
144
1
1,369,728
16
EP2S60
24,176
48,352
60,440
329
255
2
2,544,192
36
Altera Corporation
July 2005
2–7
Nios Development Board Reference Manual, Stratix II Edition
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